High Performance, Low Power Wallace Tree Multiplier
Sharmila1, G. Tejaswi2, Hrithik Sidharth3, Shilpa Reddy4
1Dr. Sharmila Vallem, Professor, Department of Electronics and Communications Engineering, Vignana Bharathi Institute of Technology, Hyderabad (Telangana), India.
2G. Tejaswi, Students, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad. (Telangana), India.
3Hrithik Sidharth, Students, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad. (Telangana), India.
4Shilpa Reddy, Students, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad. (Telangana), India.
Manuscript received on 10 May 2023 | Revised Manuscript received on 27 May 2023 | Manuscript Accepted on 15 July 2023 | Manuscript published on 30 July 2023 | PP: 20-25 | Volume-12 Issue-2, July 2023 | Retrieval Number: 100.1/ijrte.B76850712223 | DOI: 10.35940/ijrte.B7685.0712223
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multipliers. To enhance the performance of circuits and systems, the design of multipliers is very important. The key feature of a high-performance Wallace tree multiplier lies in its efficient reduction of partial product additions. By utilising a combination of carry-save and carry-propagate adders, it minimises the critical path delay and maximises the speed of multiplication. Additionally, advanced optimisation techniques such as parallel prefix adders and parallel carry-save adders can be employed to further improve performance.
Keywords: Wallace Tree Multiplier, Carry save adder, Majority Gate Adders (MGA), low power, Cadence virtuoso tool.
Scope of the Article: VLSI Algorithms