High Performance Robust Keeper Design Technique for Wide Fan-In Domino OR Logic Using CNTFET 16nm Node Technology
Balaji Ramakrishna S1, Aswatha A R2
1Balaji Ramakrishna S Department of VLSI Design and Embedded Systems from Visvesvaraya Technological University (VTU)-India.
2Aswatha A R Department of Science Degree from B.I.T.S. Pilani.
Manuscript received on 02 March 2019 | Revised Manuscript received on 08 March 2019 | Manuscript published on 30 July 2019 | PP: 1150-1158 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1726078219/19©BEIESP | DOI: 10.35940/ijrte.B1726.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper deals with the proposed adaptable threshold keeper & dynamic buffer technique(ATKDB) for CNTFET based wide fan in domino OR logic which simultaneously reduces the average power and propagation delay of the wide fan in logic implementationcompared to various dominogatetopologies.The proposed technique provides adaptable threshold voltage for the keeper transistor by means of a designed body bias generator which drives thebulk of the keeper and there by regulates the power. The design also includes a dynamic buffer at the output node to reduce pre-charge phase power consumption. With this technique, threshold voltage for keeper device is varied dynamically to reduce the contention current and clock loading. The proposed system was tested for 16 and 32 input domino gate using 16nm CNTFET model andthesatisfactoryresults w.r.t power and delay wereobtained.
Index Terms: Body Bias Generator, CNTFET Logic, Domino Logic, Delay, PDP, Power
Scope of the Article: High Performance Concrete