Energy Efficient Digital Circuit Based on Self Cascoding Positive Feedback Adiabatic Logic for Low Power VLSI Design
Vivek Jain1, Sanjiv Tokekar2, Vaibhav Neema3

1Vivek Jain, Research Scholar, Department of E&TC, IET-DAVV, Indore (Madhya Pradesh), India.
2Sanjiv Tokekar, Professor, Department of E&TC, IET-DAVV, Indore (Madhya Pradesh), India.
3Vaibhav Neema,  Assistant Professor, Department of E&TC, IET-DAVV, Indore (Madhya Pradesh), India.
Manuscript received on 12 October 2019 | Revised Manuscript received on 21 October 2019 | Manuscript Published on 02 November 2019 | PP: 950-954 | Volume-8 Issue-2S11 September 2019 | Retrieval Number: B11570982S1119/2019©BEIESP | DOI: 10.35940/ijrte.B1157.0982S1119
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Abstract: Emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. The continuing decrease in feature size and corresponding increase in chip density and operating frequency have made power consumption as a prime concern in VLSI design. For ultra low power applications, the idea of self cascode positive feedback adiabatic logic (SC-PFAL) has reported as a promising candidate to reduce power dissipation at low operating frequency. To enhance the energy efficiency of the logic circuits, self cascoding of transistor is applied to charge recovery logic working in sub-threshold region. Based on this proposed technique, we design a basic MOS digital library cell. Simulation results are found using 70nm technology model file available from predictive technologies. At low clock frequency, the proposed logic i.e. SC-PFAL has significant improvement in terms of energy consumption than original PFAL.
Keywords: Charge Recovery Logic, PFAL, Self Cascode, Ultra Low Power.
Scope of the Article: Low-power design