Verification of Accessibility and Connectivity of Multi-Die Module Through TAP Interface
Bhagyashree Atharga1, Anurag Chandan2, Sujatha Hiremath3
1Bhagyashree Atharga, Department of Engineering and Communication Engineering, RV College of Engineering, Bengaluru, Karnataka.
2Anurag Chandan, DFX-BGL, AMD India Pvt. Ltd. Bengaluru, Karnataka.
3Sujatha Hiremath, Assistant Professor, Department of Engineering and Communication Engineering, RV College of Engineering, Bengaluru, Karnataka.

Manuscript received on 09 April 2019 | Revised Manuscript received on 13 May 2019 | Manuscript published on 30 May 2019 | PP: 2077-2082 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1869058119/19©BEIESP
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Abstract: In the recent years, there is advancement in the SoC (System on Chip) designs along with the rapid evolution in the technology scaling. SoC Package may include multiple chips, semiconductor dies, core components with many system management blocks and multiple IP (Intellectual Property) cores with identical or different functionality integrated onto the single integrated chip (IC). In present days, when compared to the MCM (Multi-chip Module) multiple dies are fabricated onto the single package which collectively account for achieving several goals accounting for less manufacturing cost. The complex design requires structured and novel way of testing the structural interconnects. Therefore, TAP (Test Access Port) interface proves to be simpler and efficient. This is carried out by employing the three standards, IEEE 1149.1, IEEE 1687, IEEE 1500 at different levels of SoC which modularize the testing mechanism in an efficient way. Thus, the structural testing must be performed at chip level as well as SoC level to ensure proper interconnection between the IPs and the multiple dies respectively. This paper presents the test access configuration for accessibility verification from Package level to down the hierarchy to IP cores through MTAP (Master-TAP) controller and structural interconnects among dies. The intention is to ensure internal registers through several modes of connections. Among the modes discussed, we can observe that the number of clock cycles required for bypass mode and broadcast mode is 24% and 26% reduced respectively. Also, prior detection of number of dies present in the SoC adds the advantage at platform-based testing reducing the testing time to the greater extent.
Index Terms: Design for Testability, IEEE 1149.1, IEEE 1500, IEEE P1687, Multi-Die Module

Scope of the Article:
Interface Agents