A New Topology on Twenty one level Inverter with Reduced Number of Switches
Ahalya. R
Ahalya R, Department of Electrical and Electronics, PRIST University, Thanjavur, India.
Manuscript received on 16 March 2019 | Revised Manuscript received on 22 March 2019 | Manuscript published on 30 July 2019 | PP: 1230-1233 | Volume-8 Issue-2, July 2019 | Retrieval Number: A1868058119/19©BEIESP | DOI: 10.35940/ijrte.a1868.058119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Multilevel inverters are known for their high power capability and reliability. They produce the output in the form of staircase waveform. If the number of level increases then almost perfect sine wave can be attained at the output. The increase in number of levels improves the power quality but it also increases the complexity in control and cost, which will increase the switching losses also. Hence there is a need for research in the multilevel inverter topology to have reduced number of switches for increased levels than the conventional and pre-proposed topologies. The purpose of this paper is to design the new topology on multilevel inverter with reduced switching devices.
Index Terms: Multilevel Inverter (MLI) Topology, Power Electronic Switches, Reduced THD
Scope of the Article: Nano electronics and Quantum Computing