High Speed ALU Design using Vedic Neurons for Energy Efficient Sensor Nodes
Saji. M. Antony1, S. Indu2, Rajeshwari Pandey3
1Saji. M. Antony, Research Scholar, Department of Engineering and Communication Engineering, Delhi Technological University, New Delhi. Assistant Professor, Department of Engineering and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, New Delhi. India.
2Dr. S. Indu, Professor, Department of Engineering and Communication Engineering, Delhi Technological University, New Delhi. India.
3Dr. Rajeshwari Pandey, Professor, Department of Engineering and Communication Engineering, Delhi Technological University, New Delhi. India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 13 May 2019 | Manuscript published on 30 May 2019 | PP: 1085-1090 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1372058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Achieving low power consumption is a major challenge in designing any wireless sensor node. In a sensor node, major domains of power consumption are during Sensing, Communicating and information processing. Sensor nodes consume maximum power during data communication. Energy consumption for processing data is very less compared to energy consumption for communication of data. So, processing data locally at each node in a sensor network, is important for minimizing power consumption. High processing speed and low area designs are in ever growing demand. In order to predict outcomes, based on previous inputs, ALU can be designed with neurons. Processing speed of ALU can be improved by replacing conventional multipliers with Vedic multipliers. This paper suggests implementation of high speed ALU using Vedic Neurons. Proposed design has been simulated using Active HDL and Xilinx ISE in order to compare with existing conventional ALU. The analysis of the results shows that the proposed design leads to reduction in the delay and reduction in LUT count (an indicator of area) of the ALU.
Index Terms: Artificial Neural Networks, Vedic Algorithm, Urdhava Triyakbhyam, Vedic Neuron, ALU Design.
Scope of the Article: Algorithm Engineering