Design and Implementation of Vedic Multiplier
Akshay Savji1, Shruti Oza2

1Akshay Savji, Department of Electronics Engineering, BV(DU)COE, Pune, India.
2Shruti Oza, Department of E&TC Engineering, BV(DU)COE, Pune, India.
Manuscript received on March 12, 2020. | Revised Manuscript received on March 25, 2020. | Manuscript published on March 30, 2020. | PP: 3142-3145 | Volume-8 Issue-6, March 2020. | Retrieval Number: F8808038620/2020©BEIESP | DOI: 10.35940/ijrte.F8808.038620

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Abstract: The ancient vedic mathematics has a set of 16 sutras and 13 subsutras. These sutras give suitable method for arithmetic calculations. The vedic formulas requires less time than the regular formulas or method of calculations [1]. Multiplier is an important block in many digital systems. This paper presents a 32-bit vedic multiplier using Urdhva Tiryagbhyam sutra of ancient vedic mathematics. The 32-bit vedic multiplier is implemented using 16-bit multipliers and adders. The 16-bit multipliers are basic blocks in the design by which the input bits are multiplied and their result are added by using the adders. The vedic multiplier can be used in many fast computing processors because of their less time delay and less number of slice LUTs. The result discusses the delay and number of slice LUTs for the implemented 32-bit multiplier. The paper also discusses the methodology of implementation.
Keywords: Urdhva Tiryagbhyam, Vedic Mathematics, Vedic Multiplier, VHDL, Xilinx Spartan-6 FPGA.
Scope of the Article: Applied Mathematics and Mechanics.