An Energy Efficient Binary Magnitude Comparator for Nanotechnology Applications
Divya Tripathi1, Subodh Wairya2

1Divya Tripathi*, Electronics & Communication Engineering, Lucknow, India.
2Subodh Wairya, Electronics & Communication Engineering, Lucknow, India.
Manuscript received on February 12, 2020. | Revised Manuscript received on February 21, 2020. | Manuscript published on March 30, 2020. | PP: 430-436 | Volume-8 Issue-6, March 2020. | Retrieval Number: F7000038620/2020©BEIESP | DOI: 10.35940/ijrte.F7000.038620

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Abstract: Quantum-dot cellular automata (QCA) is inventive nanotechnology that suggest lesser size, lesser power consumption, with more rapid speeds and deliberated as a clarification to the scaling difficulties with CMOS technology. Physical bounds of CMOS for instance the effects of quantum and the limits of technologies like power dissipation obstruct the motion of microelectronics using consistent circuit scaling. In this paper, a 1-bit binary magnitude comparator circuit is proposed that takes down the count of QCA cells related to the previously reported design’s cell numbers. The proposed course of study involves just around 29 % of the total area as compared to the preceding design with the lesser speed and clocking cycle performance and energy dissipation also. QCA designerE tool is used for simulation and finding the parameters also. The projected magnitude comparator also compares the metrics result with some of the other preceeding patterns.
Keywords: CMOS, QCA, cell, QCA designer E tool.
Scope of the Article: IoT Applied for Digital Contents.