Adjustable PRPG for Low Power Test Patterns
B. Nadimulla1, S. Aruna Mastani2

1B. Nadimulla, M.Tech, VLSI System Design, Jawaharlal Nehru Technological University, Anantapuramu (AP), India.
2Dr. S. Aruna Mastani, Department of ECE, Jawaharlal Nehru Technological University, Anantapuramu (AP), India. 

Manuscript received on March 06, 2020. | Revised Manuscript received on March 18, 2021. | Manuscript published on March 30, 2021. | PP: 195-201 | Volume-9 Issue-6, March 2021. | Retrieval Number: 100.1/ijrte.F5500039621 | DOI: 10.35940/ijrte.F5500.039621
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Abstract: As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C. 
Keywords: Pseudo Random Pattern Generator (PRPG), Linear Feedback Shift Register (LFSR), Pre-Selected Toggling (PRESTO).