Hardware-Efficient Decimation Filter Design of Zero-IF Receiver for Wireless Network
K. Srivatsan1, NithyaVenkatesan2
1First Author Name, K. Srivatsan is with the School of Electronics Engineering, VIT Chennai 600127, (Tamil Nadu). India.
2Second Author Name, Nithya Venkatesan is with the School of Electrical Engineering, VIT Chennai 600127, (Tamil Nadu) India.
Manuscript received on 17 April 2019 | Revised Manuscript received on 22 May 2019 | Manuscript published on 30 May 2019 | PP: 3044-3048 | Volume-8 Issue-1, May 2019 | Retrieval Number: A2354058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The digital scheme realized in this work emphasize on hardware-efficient decimation filter implementation along with their use in the processing of the digitized baseband signal of Zero-Intermediate Frequency (IF) Receiver. This technique allows quick selection of filter coefficients which will yield minimum error in the frequency response characteristics with less hardware complexity in terms of the number of hardware components, especially adders. The overall decimation filter is designed for Digital European Cordless Telephone (DECT) standard specifications. The performance of the entire system is analyzed by counting the number of adders used for each filter coefficient. In this simulation, it is proved that this type of design requires only 15 adders, which is less than 14.2% for droop correction filter and 40% for the Half-band filter.
Index Terms: Decimation, Digital Filter, Half-Band filter, Sigma–Delta Conversion, Wireless Communications.

Scope of the Article: Wireless Communications