Area and Power Budget Estimation of Hierarchical Network Topology in Comparison with 2D Mesh Topology for NOCs and its Design and Implementation Oriented Overview
Kulkarni Rashmi Manik1, S Arulselvi2, B Karthik3

1Kulkarni Rashmi Manik, Research Scholar/ECE, Bharath Institute of Higher Education and Research, Chennai, (Tamil Nadu), India.
2S Arulselvi, Associate Professor, Department of ECE, Bharath Institute of Higher Education and Research, Chennai, (Tamil Nadu), India.
3B Karthik, Associate Professor, Department of ECE, Bharath Institute of Higher Education and Research, Chennai, (Tamil Nadu), India.

Manuscript received on 13 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 135-141 | Volume-7 Issue-6, March 2019 | Retrieval Number: F2145037619/19©BEIESP
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Abstract: Today’s IC (Integrated Circuit) fabrication technology allows us, integration of billions of transistors on a single chip. The trend in design of SoCs (System-On-Chips) for mobile phones as well as high end servers is to integrate multiple processor cores with other peripheral cores for achieving higher performance. The other cores integrated along with processor cores are generally, graphics processing units, memory controllers, encryption/decryption cores, special functional units, accelerators and various types of interface controllers. As the number of processor cores (as a masters) increase beyond 16, the bus-based architecture poses bottleneck to overall performance. The network-on-chip based interconnects topology (using packet switching) promises higher performance for complex multi-core SoCs. The NoC (network-on-chip) interconnect design involves design of (a) network adaption logic for all cores, (b) on chip routers and (c) topology. The various network topologies have been proposed and analyzed for NoC. The problem of arriving at perfect Network topology and efficient router architecture for integrating 64 cores has been analyzed in this research work. As the low power SoC architectures are gaining importance, the reduction in power budget for NoC gains more attention of researchers. The power-wise exploration of topology with NoC power estimation tool can help in achieving low power targets. The proposed Modular Network Topology is compared with 2-D (Two Dimension) mesh topology. Standard Orion3 tool is used for estimating router power and area considering 45nm and 65nm technologies. Results are encouraging and better in performance than regular 2-D mesh topology. In this research article, we tried to give thought for gate level design and implementation of NOC. For that, we considered 64 processing elements connected with hierarchical networking topology. With implementation of GALS, feasibility study is carried out. Mainly we concentrated on cross bar router design which is a basic element of NOC.
Keywords: Network on Chip (NoC), Network Topology, System-on-chip (SoC), Integrated Circuit (IC), ASM (Algorithmic State Machine), GALS (Globally Asynchronous Locally Synchronous), and NIC (Network Interface Component).
Scope of the Article: Sensor Networks, Actuators for Internet of Things