Optimization Method for Delay and Power Using Enhanced CSS FLIP FLOP with 24 Transistors
G. Ravi Kishore1, N. M. Nandhitha2

1G. Ravi Kishore, Research Scholar, Sathyabama University, Chennai (Tamil Nadu), India.
2Dr. N. M. Nandhitha, Research Supervisor Professor & Dean, Department of EEE, Sathyabama University, Chennai (Tamil Nadu), India.
Manuscript received on 23 February 2020 | Revised Manuscript received on 06 March 2020 | Manuscript Published on 18 March 2020 | PP: 116-119 | Volume-8 Issue-6S March 2020 | Retrieval Number: F10220386S20/2020©BEIESP | DOI: 10.35940/ijrte.F1022.0386S20
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: New way optimization method is an Enhanced CSS F 2A new method titled in this paper to explain the improved flip flop design with 24 transistor’s using circuit-shared static flip-flop (ECSSFlip Flop).this implementation enhances power and delay where we utilize 5 NOR gates and 2 INV’s(inverters), these methods are these methods are utilized in the quality cell libraries, The ECSS FLIP FLOP utilizes a positive intercessor clock signal, it is produced from a main clock, to require information into a main latch and a negative fringe of the foundation clock to carry the info during a gated latch. Cadence(Virtuoso) simulations at 180-μm found optimized at different frequency now the ability by a power dissipation of 9.516nW and delay by 3.634 ns in comparison to CSS FLIP FLOP.
Keywords: ECSS FLIP FLOP, FLIP FLOP ( F2 ), Power, Delay, Gate.
Scope of the Article: Low-power design