Data Aware Dynamic Low Power Reconfigurable FIR Filter Design
M. Bharath Reddy1, M. Sai Sarath Kumar2, B. Suresh Kumar3
1M.Bharath Reddy, M. Tech (VLSI Design), VIT University/Vellore Institute Of Technology/ VIT University, Vellore (Tamil Nadu), India.
2M.Sai Sarath Kumar, M. Tech (VLSI Design), VIT University/Vellore Institute Of Technology/ VIT University, Vellore (Tamil Nadu), India.
3B.Suresh Kumar, M. Tech (VLSI Design), VIT University/Vellore Institute Of Technology/ VIT University, Vellore (Tamil Nadu), India.
Manuscript received on 20 March 2014 | Revised Manuscript received on 25 March 2014 | Manuscript published on 30 March 2014 | PP: 150-152 | Volume-3 Issue-1, March 2014 | Retrieval Number: F0902012614/2014©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper aims for developing a new architecture for finite impulse response (FIR) filter, which will reduce dynamic power consumption based on the concept of dynamic filter order change. The dynamic changing of the filter order is based on the fact that FIR filter has large amplitude variations in both the input sequence and impulse response (filter coefficients). Trade off between filter performance and dynamic power consumption presented in this paper suggests that a significant reduction in the dynamic power can be achieved without much compromise in the filter performance. The required area overhead is also much less when compared to the conventional approach. The power savings of up to 25 to 35% can be achieved with the modified FIR filter architecture presented in this paper
Keywords: FIR filter, IIR filter, Convolution, Reconfigurability.
Scope of the Article: Low-power design