Physical IC Design Layout of Memory-Based Real Fast Fourier Transform Architecture using 90nm Technology
Rajasekhar Turaka1, M. Satya Sai Ram2
1Rajasekhar Turaka*, Research Scholar, A.N.U. College of Engineering &Technology, A.N.U. Guntur, India.
2Dr. M. Satya Sai Ram, ECE Department, RVR&JC College of Engineering, Guntur, AP, India.
Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 3681-3686 | Volume-8 Issue-5, January 2020. | Retrieval Number: E6592018520/2020©BEIESP | DOI: 10.35940/ijrte.E6592.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper we present a low complexity physical IC layout for memory based Real Fast Fourier Transform (RFFT) architecture using 90nm technology. FFT architectures are the most important algorithms in the modern communication systems like and very high bit rate digital subscriber line (VDSL) asymmetric digital subscriber line (ADSL). In this FFT algorithm is based on radix-2 decimation-in-frequency. In order to meet the real time requirements of very large scale integration (VLSI), we designed a low complexity and high speed FFT architecture. The RFFT architecture was realised using Verilog hardware description language (HDL). This architecture is simulated using Native code launch of cadence and synthesized using RTL code complier of cadence tool. Each step of application specific integrated circuit (ASIC) physical IC design flow was synthesized using cadence Innovus 90nm technology and we optimize the design to reduce the area, power and timing requirements.
Keywords: Fast Fourier Transform (FFT), real FFT, Application Specific Integrated Circuit (ASIC), Verilog HDL.
Scope of the Article: Cyber Physical Systems (CPS).