Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer
Poonam Pathak1, Rabindra Kumar Singh2
1Poonam Pathak*, Department of Electronics & Communication Engineering, School of Engineering, Babu Banarasi Das University, Lucknow, India.
2Rabinder Kumar Singh, Department of Electronics and Communication Engineering, Kamla Nehru Institute of Technology, Sultanpur.

Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 3999-4003 | Volume-8 Issue-5, January 2020. | Retrieval Number: E6423018520/2020©BEIESP | DOI: 10.35940/ijrte.E6423.018520

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Abstract: Quantum Dot Cellular Automata (QCA) is treated as a most promising technology after CMOS techniques. The major advantages of QCA techniques are faster speed, lower energy consumption and smaller size. The implementation of clocks play very big role in the effective design of QCA circuits. In this paper, a QCA circuit is designed using the concept of QCA clocks. The proposed study describes a new method of implementing the logical function with power depletion analysis. The proposed logical function uses total number of 57 cells in which the area of each cell 372 nm2. The energy dissipation in this implementation is 18.79 meV and the total acquired area is 0.192 μm2. The proposed circuit is implemented utilizing QCA Designer. The proposal is excellent in the realization of nano-scale computing with minimal power utilization. The results are compared with the existing approaches and improvements of 6% in the area required and 7% in the number of cells are achieved.
Keywords: QCA, Single Electron Tunneling (SET), Complementary Metal-Oxide-Semiconductor (CMOS), QCA Designer, Tunnel Phase Logic (TPL).
Scope of the Article: Nanometer-scale Integrated Circuits.