Analysis of Clock trees for optimization through Multi point Clock Tree Synthesis
Papisetty Veera kishore1, S. Aruna Masthani2, Dumpala Raghuveer Reedy3, Kasturi Suresh4
1Papisetty Veera Kishore, VLSI System Design, M Tech, JNTU Anantapur, Andhra Pradesh, India.
2Dr.S.Aruna Masthani, Assistant professor Department of ECE, JNTUA College of Engineering Anantapur (JNTUACEA), Anantapur, India.
3Dumpala Raghuveer Reedy, SMTS Silicon Design Engineer, AMD India Pvt Ltd, India.
4Kasturi Suresh, Senior Silicon Design Engineer, AMD India Pvt Ltd India.

Manuscript received on January 02, 2020. | Revised Manuscript received on January 15, 2020. | Manuscript published on January 30, 2020. | PP: 1879-1882| Volume-8 Issue-5, January 2020. | Retrieval Number: E6169018520/2020©BEIESP | DOI: 10.35940/ijrte.E6169.018520

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Abstract: With rapid development of deep submicron (DSM) VLSI circuits design, building clock tree with minimal insertion delays and minimal skews has turned out to be challenging. In this Paper for a given specified block with a latency of 530 ns it is aimed to achieve a latency of 400ns and achieve optimal power. Here a Clock Tree Synthesis method is used to reduce the latency and obtain the timing closure for the given block. The analysis is made and compared in terms of clock skew and insertion delay by varying the tap points. In this process of achieving the timing closure it is observed power has optimized by selecting the appropriate tap points.
Keywords: The Analysis is Made and Compared in Terms of Clock Skew and Insertion Delay By Varying The Tap Points.
Scope of the Article: Predictive Analysis.