High Level Synthesis of VLSI based Image Scaling Architecture for High Definition Displays
Chidadala Janardhan1, Kota Venkata Ramanaiah2, K Babulu3
1Chidadala Janardhan, Research Scholar, Department of E.C.E.JNTUK University, Kakinada, (Andhra Pradesh), India.
2Dr. Kota Venkata Ramanaiah, Associate Professor, Department of E.C.E,Y.S.R College of Yogi Vemana University, Proddatur, (Andhra Pradesh), India.
3Dr. K Babulu, Professor, Department of E.C.E, JNTUK University Kakinada, (Andhra Pradesh), India.
Manuscript received on 24 January 2019 | Revised Manuscript received on 30 March 2019 | Manuscript published on 30 January 2019 | PP: 350-355 | Volume-7 Issue-6, March 2019 | Retrieval Number: E2077017519©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Due to rapid advancements in multimedia technology from consumer electronics to medical imaging, HDTV display systems image scale up/down process is necessary for efficient displaying entire scene without loss of its original quality. The edge oriented based image processing plays the major role in the Image processing technique. The current real time applications demands low complexity, low cost and high performance devices for portable applications and it is achieved through CMOS-VLSI technology. This paper presents an efficient approach for edge-oriented image scaling processor Technique with low power and low complexity VLSI architecture design for edge-oriented area of image pixel scaling technique. This paper approaches the horizontal scaling and vertical scaling processor technique for improving the size of the image with better image quality than the existing image scaling processor. The horizontal and vertical image scaling processor technique is implemented in the proposed technology in order to improve the input image size of 400 X 400 image into 800 X 800 with better image quality. The Proposed five stage VLSI architecture consists of three phases such as edge orientation, vertical scaling and horizontal pixels scaling blocks respectively. Then, this proposed edge oriented image scaling technique is implemented in the VHDL and synthesized in the XILINX ARTIX-7 FPGA and shown the comparison for power, area and delay reports.
Keywords: Bilinear, FPGA, HDTV display, Image scaling,
Scope of the Article: Image Security