Performance Evaluation of Re-Configurable VLSI Architecture based on Finite Impulse Response Interpolation Filter
Raja Krishnamoorthy1, P.T. Kalaivaani2, Puvirajan Thirumurugan3
1Raja Krishnamoorthy, Professor, Department of ECE, CMR Engineering College, Kandlakoya Villaga, Hyderabad (Telangana), India.
2P.T. Kalaivaani, Associate Professor, Department of ECE, Vivekanandha College of Technology for Women, Tiruchengode, Namakkal (Tamil Nadu), India.
3Puvirajan Thirumurugan, Assistant Professor, Department of Electronics and Communication Engineering, CMR Engineering College, Kandlakoya Villaga, Hyderabad (Telangana), India.
Manuscript received on 17 December 2018 | Revised Manuscript received on 28 December 2018 | Manuscript Published on 09 January 2019 | PP: 484-491 | Volume-7 Issue-4S November 2018 | Retrieval Number: E2076017519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The implementation of a two-stage improvement procedure for modelling a reconfigurable VLSI Structure .In this work an Finite-impulse -response interpolation filter and the Multi-standard digital up converter(DUC) are used to reduce limit its power and area consumed in the proposed .In this strategy is mainly minimize the number of multiplications for every input samples with an addition of each samples are compared with the individual applied in each standard filter. While design the specific usage of each level root-raised-cosine conduit and FIR filter with multi standard DUC are determined with three different stages. During the supplementary period, a two-bit based Binary common sub expression (BCS) based eliminating algorithm are presented in this model for providing effective constant multiplier ,which are all fundamental components for various filters. This methodology has been effectively perform with minimizing the area and the power consumption of the system ,with progress an operating frequency of a three-bit Binary common sub-articulation (BCS) technique details are provided in this study, along with the better performance an modelling of multi-standard Digital up converter are Efficiently used in VLSI architecture.
Keywords: Root-Raised-Cosine, Digital Up Converter (DUC), FIR Interpolation Filter, Coefficient Sector Generation Module (CG).
Scope of the Article: VLSI Algorithms