A Double Tail Dynamic Latched Comparator for Pipelined ADC
K. Lokesh Krishna1, A. Krishna Mohan2, Yahya Mohammed Ali Al-Naamani3

1K. Lokesh Krishna, Department of ECE, S. V. College of Engineering, Tirupati (Andhra Pradesh), India.
2A. Krishna Mohan, Department of ECE, S. V. College of Engineering, Tirupati (Andhra Pradesh), India.
3Yahya Mohammed Ali Al-Naamani, Department of ECE, Mewar University, Gangarar (Rajasthan), India.
Manuscript received on 13 February 2019 | Revised Manuscript received on 04 March 2019 | Manuscript Published on 08 June 2019 | PP: 200-203 | Volume-7 Issue-5S4, February 2019 | Retrieval Number: E10380275S419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Data converter circuits are very essential circuit blocks in the implementation of low power and moderate speed electronic systems. In recent years, with more and more portable electronic systems being designed, developed and available in the market, it becomes essential to include more features in these systems. One of the main blocks in these systems is analog to digital converter, which uses a comparator inside it. With the purpose of improving the functionality of ADC circuit, a complete design and simulation. The comparators use regenerative feedback to convert the output to a full scale digital signal. The main parameters considered are power dissipation, gain, propagation delay, offset voltage and slew rate. The simulation is carried out in CMOS 90nm technology using spectre of cadence EDA tool. The simulation results permit the analog circuit designer to completely explore the tradeoffs such as operating speed and power consumption for flash ADC architecture. The power dissipation of the designed comparator circuit is 136µW, when operated at supply voltage of 1.2V and delay is simulated to be 526ps. The simulated results show that it can be used for a pipelined ADC architecture.
Keywords: CMOS; Low offset; Low Power; Mixed Signal Circuit and Slew Rate.
Scope of the Article: Low-power design