A Reduced Latency Architecture for Obtaining High System Performance
Kareemullah Shaik1, Mohammad Mohiddin2, Md. Zabirullah3
1Kareemullah shaik, M. Tech. Student, Shadan College of Engineering and Technology, Affiliated JNTU, Hyderabad (Telangana), India.
2Mohammad Mohiddin, M. Tech. Student, Shadan College of Engineering and Technology Affiliated, JNTU, Hyderabad (Telangana), India.
3Md. Zabirullah, B.Tech Student, Royal Institute of Technology and Sciences, Affiliated JNTU, Hyderabad (Telangana), India.
Manuscript received on 18 November 2012 | Revised Manuscript received on 25 November 2012 | Manuscript published on 30 November 2012 | PP: 1-5 | Volume-1 Issue-5, November 2012 | Retrieval Number: E0334101512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Microprocessor performance has improved rapidly these years. In contrast, memory latencies and bandwidths have improved little. The result is that the memory access time has been a bottleneck which limits the system performance. As the speed of fetching data from memories is not able to match up with speed of processors. So there is the need for a fast memory controller. The responsibility of the controller is to match the speeds of the processor on one side and memory on the other so that the communication can take place seamlessly. Here we have built a memory controller which is specifically targeted for SDRAM. Certain features were included in the design which could increase the overall efficiency of the controller, such as, searching the internal memory of the controller for the requested data for the most recently used data, instead of going to the Memory to fetch it. The memory controller is designed which compatible with Advanced High-performance Bus (AHB) which is a new generation of AMBA bus. The AHB is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripherals.
Keywords: SDRAM, Memory Controller, AMBA, FPGA, Xilinx, Modelsim.
Scope of the Article: High Performance Computing