Design and Implementation of Energy Efficient Power Gated MALFA Cell
K. Murugan1, S. Baulkani2
1K. Murugan, Department of Electronics and Communication Engineering, Dr.Sivanthi Aditanar College of Engineering, Anna University, Tamil Nadu, India.
2S. Baulkani, Department of Electronics and Communication Engineering, Government College of Engineering, Tirchy, Anna University, Tamil Nadu, India. 

Manuscript received on November 15, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on November 30, 2019. | PP: 1178-1181 | Volume-8 Issue-4, November 2019. | Retrieval Number: D6926118419/2019©BEIESP | DOI: 10.35940/ijrte.D6926.118419

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Abstract: Power gating is one of the power reduction techniques that is mostly suitable for low power VLSI applications. It reduces the power consumption by shutting of the current to the blocks not in use. Hybrid power gating is applied to Modified Adiabatic Logic based Full Adder (ALFA) cell. The proposed ALFA cell reduces the energy consumption by 67.21%, 51.31%, 55.86% and 27.01% when compared to CMOS FA, PTL with TG 16T, hybrid CMOS and PTL with TG 14T. ALFA cell with hybrid power gating technique reduces the power consumption by 1.76, 2.08%, 1.13%, 1.44%, 0.48% and delay by 5.92%, 11.19%, 11.19%, 5.92%, 24.92% when compared to ALFA cell with NMOS sleepy approach, PMOS sleepy approach, PMOS sleepy stack approach, NMOS sleepy stack approach and dual stack approach.
Keywords: ALFA Cell, Hybrid Power Gating, Sleep Transistor, Stacking Approach.
Scope of the Article: Expert Approaches.