Delay Minimization in on Chip Interconnects by the Method of Logical Effort
S.A.Sivasankari1, B.Sakthi Kumar2, R.Ohmsakthi Vel3
1S.A.Sivasankari, Assistant Professor, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P., India.
2B.Sakthi Kumar, Assistant Professor, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P., India.
3R.Ohmsakthi Vel, Assistant Professor, Department of Mechatronics Engineering, Agni College of Technology, Chennai, Tamilnadu, India.
Manuscript received on November 20, 2019. | Revised Manuscript received on November 28, 2019. | Manuscript published on 30 November, 2019. | PP: 7098-7102 | Volume-8 Issue-4, November 2019. | Retrieval Number: D5242118419/2019©BEIESP | DOI: 10.35940/ijrte.D5242.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The ultimate aim of the work is to minimize the delay in on-chip interconnects. Our objective is to analyze the wire geometry impact for delay minimization. Here proposed effect is achieved by Logical effort(LE).The analyzes which is on the low swing where it was implemented by using CMOS circuit in 90 nm GPDK library and simulations on the cadence virtuoso ADE EDA tools. Once by reducing the delay the application is oriented for high speed applications. The logical effort (LE) model which reduces the delay minimization. This work which compensates both the long interconnects and short interconnects.
Keywords: Interconnects, Inductive effects, Wire geometry, Crosstalk, Transmission line, Logical effort.
Scope of the Article: Artificial Intelligent Methods, Models, Techniques.