Design of Low Power Memory Architecture using 10t Sram Array
M. Madhumalini1, B. Saranraj2
1M. Madhumalini, Assistant Professor, Department of Electronics and Communication Engineering, P. A. College of Engineering and Technology.
2B. Saranraj, Assistant Professor, Department of Electronics and Communication Engineering, P. A. College of Engineering and Technology.
Manuscript received on November 11, 2019. | Revised Manuscript received on November 20 2019. | Manuscript published on 30 November, 2019. | PP: 10650-10653 | Volume-8 Issue-4, November 2019. | Retrieval Number: D4264118419/2019©BEIESP | DOI: 10.35940/ijrte.D4264.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.
Keywords: SRAM, Conducting pmos, Sleep Transistor, Decoder, pre-charge, sense Amplifier.
Scope of the Article: Computer Architecture and VLSI.