Image Denoising using FPGA Based 2D-DWT Architecture
Naseer M. Basheer1, Mustafa Mushtak Mohammed2

1Dr. Nasseer M. Basheer, Department of Computer Engineering, Technical College, Mosul, Iraq.
2Mr. Mustafa Mushtak Mohammed, Department of Computer Engineering, Technical College, Mosul, Iraq.

Manuscript received on 21 September 2013 | Revised Manuscript received on 28 September 2013 | Manuscript published on 30 September 2013 | PP: 92-97 | Volume-2 Issue-4, September 2013 | Retrieval Number: D0789092413/2013©BEIESP
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Abstract: In this work, a simple design is implemented for removing noise from gray scale images, that depends on Two Dimensional Discrete Wavelet Transform (2D-DWT) and a threshold stage. The proposed design is used to remove two types of noise (the Salt and pepper noise, and the Gaussian noise) from the corrupted images. The proposed architecture is based on lifting scheme approach using the (5/3) wavelet filter. This architecture consists of a control unit, a processor unit, two on-chip internal memories to speed up system operations, and an on-board off-chip external memory (Intel strata parallel NOR flash PROM). The proposed architecture is designed and synthesized with the VHDL language and then implemented on the FPGA Spartan 3E starter kit (XC3S500E) to check validation of the results and performance of the design.
Keywords: Two Dimensional Discrete Wavelet Transform (2D- DWT), Image Denoising, lifting Scheme, (5/3) wavelet Filter, and FPGA Applications.

Scope of the Article: Image analysis and Processing