Performance Evaluation of New Adder Designed for Electronic Circuits
R.Gowrishankar1, N.Sathishkumar2, B.Senthilkumar3

1R.Gowrishankar, Department of Electronics and Communication Engineering, KIT- Kalaignarkarunanidhi Institute of Technology, Coimbatore, India.
2Dr.N.Sathishkumar, Department of Electronics and Communication Engineering,, Sri Ramakrishna Engineering Collegey, Coimbatore, India.
3Dr.B.Senthilkumar, Department of Electronics and Communication Engineering, KIT-Kalaignarkarunanidhi Institute of Technology, Coimbatore, India.

Manuscript received on 08 August 2019. | Revised Manuscript received on 14 August 2019. | Manuscript published on 30 September 2019. | PP: 5039-5043 | Volume-8 Issue-3 September 2019 | Retrieval Number: C5681098319/2019©BEIESP | DOI: 10.35940/ijrte.C5681.098319
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Abstract: Arithmetic and Logic Unit (ALU) is the important module in any digital system utilized in the current world applications. Adder plays major role in the construction of any ALU. Multipliers can also be designed with the help of continuous addition. The efficient design of adders is very much needed for the efficient ALU design. Parallel prefix adder has been chosen in this research because of its fastest computation and efficiency. Kogge Stone, Sklansky, Ladner Fischer, Brunt Kung, Han-Carlson and Knowles are the adders discussed in this research. Further, the combinations of any two adders have also been tested for the best efficiency in terms of power consumption and delay utilisation. From the many combinations, it is found that the proposed combination of Bruntkung and SKlansky (BSK) adder performs excellent with the power consumption of 25011.22 nW and delay of 1243 pS.
Keywords: Adder, Delay, Multiplier, Power.

Scope of the Article:
High Performance Computing