Implementation of Low Power Carry Skip Adder using Reversible Logic
Addanki Purna Ramesh

1Addanki Purna Ramesh *, Professor, Department of ECE, Vishnu Institute of Technology, Bhimavaram, India.
Manuscript received on 1 August 2019. | Revised Manuscript received on 9 August 2019. | Manuscript published on 30 September 2019. | PP: 2825-2832 | Volume-8 Issue-3 September 2019 | Retrieval Number: C5212098319/2019©BEIESP | DOI: 10.35940/ijrte.C5212.098319
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Abstract: Addition is a vital arithmetic operation. It is the base of commonly used arithmetic operations such as division, subtraction, and multiplication. Adder is a digital circuit that accomplishes addition of numbers. The one bit full adder is the basic block of an arithmetic unit. There are several adder designs implemented so far to reduce the power. However, each design suffers from exact drawback. Reversible logic is the growing technology in the current era. The numbers of input and output lines in reversible logic are equal. In reversible logic the inputs are to be recovered from the outputs. Reversible logic gates are defined by the user. In this paper Carry Skip Adder (CSKA) is implemented in two different designs i.e. design-I and design-II. Design-I is implemented using Peres gates with irreversible (XOR, AND, OR) logic gates. Design-II is implemented using PERES, TOFFOLI, and FREDKIN reversible logic gates. Design-I and design-II designs are synthesized and simulated by Mentor Graphics tool. Design-II is more efficient in terms of transistor count and power consumption compared to Design-I.
Keywords— Reversible Logic Gates, Carry Skip Adder, Power Consumption.

Scope of the Article:
Low-power design