Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications
A.Anitha1, S. Rooban2, M. Sujath3
1A. Anitha, Sr. Assistant Professor in the Department of Electronics and Communication Engineering, CVR College of Engineering, Telangana, India.
2Dr. S. Rooban, Associate Professor, Department of Electronics and Communication Engineering, KLEF, Vijayawada (Andhra Pradesh), India.
3Dr. M. Sujatha, Chair Person, Research Program Academic Council and Professor in the Department of Electronics and Communication Engineering, KLEF, Vijayawada (Andhra Pradesh), India.
Manuscript received on 6 August 2019. | Revised Manuscript received on 11 August 2019. | Manuscript published on 30 September 2019. | PP: 3327-3332 | Volume-8 Issue-3 September 2019 | Retrieval Number: C4982098319/2019©BEIESP | DOI: 10.35940/ijrte.C4982.098319
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In today’s electronic sector, low energy has appeared as a major feature. Power effectiveness is one of the most significant characteristics of contemporary, high-speed and mobile digital devices. Different methods are available to decrease energy dissipation at distinct stages of the planning method and have been applied. As the transistors count per device region continues to rise, while the switching energy does not rise at the same pace, power dissipation increases, and heat removal becomes more hard and costly. The power consumption of electronic appliances can be decreased by using various logic types. For such low-power electronic applications, adiabatic logic mode is very appealing. Using adiabatic logic, distinct power-efficient gates are intended in this document and contrasted for energy dissipation, propagation delay and no of the transistors used. In addition, the circuit developer can use these gates in the combinational and sequential circuits to develop low-power systems. The simulations of these gates are carried out in 90 nm technology using cadence virtuoso instrument.
Keywords: Adiabatic Logic, CMOS Logic, Efficient Charge Recovery Logic (ECRL), Positive Feedback Logic (PAL), 2N2N2P Logic.
Scope of the Article: Energy Efficient Building Technology