Radix-10 Fixed Point Division Hardware
Diganta Sengupta1, Mahamuda Sultana2, Atal Chaudhuri3
1Diganta Sengupta, Dept. of Computer Science and Engineering, Techno International Batanagar, Kolkata, West Bengal , India.
2Mahamuda Sultana, Dept. of Information Technology, Techno International New Town, Kolkata, West Bengal , India, firstname.lastname@example.org
3Atal Chaudhuri, Vice-Chancellor, Veer Surendra Sai University of Technology, Sambalpur, Odisha , India.
Manuscript received on 5 August 2019. | Revised Manuscript received on 11 August 2019. | Manuscript published on 30 September 2019. | PP: 1443-1448 | Volume-8 Issue-3 September 2019 | Retrieval Number: C4450098319/19©BEIESP | DOI: 10.35940/ijrte.C4450.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Standardization of decimal floating-point formats by IEEE in IEEE 754-2008 Standards fuelled the interest on decimal floating-point architectures among the global research community. Although decimal arithmetic architecture research attracted computer scientists for the last two decades, the major thrust was observed past the year 2008. Multiple proposals have been witnessed for decimal arithmetic units, mostly adders/subtractors, and multipliers. Very few designs have been proposed in the division domain. This article proposes decimal division hardware based on sutras from Vedic Mathematics, the ancient mathematics system. We present a Reduced Magnitude Divisor Generator which converts each digit of the actual divisor into a reduced digit set [-5, 5] using a unique combination/modification of the Vedic Sutras. The divisor digit magnitude reduction also minimizes the product set of multiplication as the single-digit multiplier belongs to the reduced digit set [0, 5] barring the sign. The sign of the dividend or the divisor is not attended during division as a simple XOR operation on the two signs provides the sign of the quotient. Peer comparison has exhibited better results for our design in terms of space and time.
Keywords: Decimal Division, Vedic Division, Vedic Sutras, Division Architecture, Reduced Magnitude Divisor Generator, IEEE 754-2008.
Scope of the Article: Computer Architecture and VLSI