Analysis of Current Steering Digital to Analog Converter
Abhinav V. Deshpande

Mr. Abhinav V. Deshpande, Assistant Professor, Department of Electronics & Telecommunication Engineering, Prof. Ram Meghe Institute of Technology & Research, Badnera, Amravati (Maharashtra)-444701 India.
Manuscript received on 20 July 2016 | Revised Manuscript received on 30 July 2016 | Manuscript published on 30 July 2016 | PP: 24-26 | Volume-5 Issue-3, July 2016 | Retrieval Number: C1608075316©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: The current steering Digital to Analog Converter (DAC) with a Digital random return to zero technique in order to improve the namic performance is presented in this research paper. In order to demonstrate the proposed technique, an 8 bit CMOS DAC is designed and the layout is prepared in 90 nm technology. The chip layouts run on low power and have small area overhead.
Keywords: DAC, Current Steering, Converter

Scope of the Article: Structural Reliability Analysis