Dynamic Power Optimization of 32-Bit MIPS Processor Using Clock Gating for Low Power Applications
V. Prasanth1, K. Babulu2, M. Kamaraju3 
1V. Prasanth, Ph. D Scholar, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.
2K. Babulu, Professor of ECE, Jawaharlal Nehru Technological University/ Kakinada, Andhra Pradesh, India
3M. Kamaraju, Professor, Electronics and Communication Engineering Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India.

Manuscript received on 12 March 2019 | Revised Manuscript received on 17 March 2019 | Manuscript published on 30 July 2019 | PP: 5936-5942 | Volume-8 Issue-2, July 2019 | Retrieval Number: B3575078219/19©BEIESP | DOI: 10.35940/ijrte.B3575.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The demand for low power processor is increasing day by day in mobile application for video, audio, mixed signal processing, gaming console and battery-operated electronic devices. Power consumption is the main issue in batter operated devices which constantly reduces battery life. Compared to static power Dynamic power yields more power consumption in digital design. Clock power is one of the major factors in total power consumption which results in high dynamic power consumption. In this paper, a 32-bit MIPS processor is designed to maximize the performance while considering the battery life of the device. Clock gating and data gating method is adopted in this paper and to reduce dynamic power. This design is implemented on 28nm kintex-7 FPGA Board and power is analyzed
Index Terms: MIPS, Power Consumption, Dynamic Power, Clock Gating, Switching Activity.

Scope of the Article: Design Optimization of Structures