Asic Implementation of 12-Bit Radix-8 Booth Multiplier
U. Geetalakshmi1, M.V. Nageswara Rao2
1Uriti Geetalakshmi, Department of Educational Credential Evaluators, GMR Institute of Technology, Rajam, AP, India.
2M.V. Nageswara Rao, Department of Educational Credential Evaluators, GMR Institute of Technology, Rajam, AP, India.
Manuscript received on 16 March 2019 | Revised Manuscript received on 23 March 2019 | Manuscript published on 30 July 2019 | PP: 4013-4016 | Volume-8 Issue-2, July 2019 | Retrieval Number: B3181078219/19©BEIESP | DOI: 10.35940/ijrte.B3181.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers are playing a vital role in DSP and Neural Networks applications. Many methods have been introduced to work on multipliers that offer high speed, less power consumption and reduced area. Booth Algorithm demonstrates an efficient way of signed binary multiplication. In this paper, physical design of 12-bit radix-8 booth multiplier for signed multiplication is presented with an aim to improve the performance metrics such as power, area and delay. The performance of 12-bit radix-8 booth multiplier is compared with the 64-bit radix-16 booth multiplier.
Index Terms: Modified Booth Re-Coding, Partial Products, radix- 8.
Scope of the Article: Network Coding