Impact of Resistive Open Faults on Inverter Chain and 7t Sram
C.Gangaiah Yadav1, K.S.Vijula Grace2

C.Gangaiah Yadav, Research Scholar, Dept. Of Ece, Noorul Islam Centre For Higher Education, Kumaracoil, Tamil Nadu.
K.S.Vijula Grace, Assistant Professor, Dept. Of Ece,Noorul Islam Centre For Higher Education, Kumaracoil, Tamil Nadu.

Manuscript received on 1 August 2019. | Revised Manuscript received on 9 August 2019. | Manuscript published on 30 September 2019. | PP: 559-563 | Volume-8 Issue-3 September 2019 | Retrieval Number: B1783078219/19©BEIESP | DOI: 10.35940/ijrte.B1783.098319
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Abstract: An aggressive scaling of the technology and the increasing the number of the transistor counts are the major challenge of the design of the Integrated Circuit (IC). As well as interconnection lines and resistive opens have become a problem in modern nanometre technologies. The resistive open faults denote degradation in the connectivity within a circuit’s interconnects because of unavoidable manufacturing failures in both current and developing technologies. The resistive open fault is an imperfect circuit connection that can be modelled as a defect resistor between two circuit nodes. The Resistive open faults will not cause function fault immediately. But, it will cause the delay fault and cannot employ the design of voltage to survey. In this research, find the impact of resistive open fault in the 7-Transistor (7T) SRAM cell design and inverter chain. The proposed 7T SRAM cell design and inverter chain is implemented in 45nm technology with cadence library. The main objective of this proposed research work is to efficiently detect impact of resistive open faults and reduces delay and static and dynamic power of 7T SRAM cell design and inverter chain.
Keywords: Resistive Open Fault [ROF], Delay Fault, Conductivity, Inverter Chain, 7T SRAM, Cadence tool, Area, Power, Delay.

Scope of the Article: Nanometer-Scale Integrated Circuits