Low Power Design of 0.8V based 8 Bit Content Addressable Memory using MSML Implemented in 22nm Technology for Aeronautical Applications
G. Naveen Balaji1, M. Karthiga2, D. Swetha3, M. Suchitra4
1G. Naveen Balaji, Assistant Professor, Department of ECE, SNS College of Technology, Coimbatore (Tamil Nadu), India.
2M. Karthiga, Assistant Professor, Department of ECE, Vivekananda College of Engineering for Women, Tiruchengode, (Tamil Nadu), India.
3D. Swetha, UG Student, Department of Aeronautical Engineering, SNS College of Technology, Coimbatore (Tamil Nadu), India.
4M. Suchitra, UG Student, Department of Aeronautical Engineering, SNS College of Technology, Coimbatore (Tamil Nadu), India.
Manuscript received on 16 October 2019 | Revised Manuscript received on 25 October 2019 | Manuscript Published on 02 November 2019 | PP: 2688-2694 | Volume-8 Issue-2S11 September 2019 | Retrieval Number: B13290982S1119/2019©BEIESP | DOI: 10.35940/ijrte.B1329.0982S1119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Proposed Paper contains Master slave match line (MSML) architecture which is implemented in traditional Content Addressable Memory (CAM) cell for storing 8 bit of data. Objective of the proposed methodology is to improve searching speed with less power consumption. MSML operation depends on two things one is Master Match Line (MML) and slave match line (SML). Design is performed using SPICE in 22nm technology which is weightless and can be used in Aeronautical Equipment. Various parameters such as temperature, power and delay are calculated for various types of CAM cell. Proposed methodology power consumption is found to be 598mw with delay of 5.98ns for 22nm technology.
Keywords: CAM Architecture, NAND Architecture, NOR Architecture, MSML Design.
Scope of the Article: Low-power design