A CMOS Class-E Cascode Power Amplifier for GSM Application
Manoj Sharadrao Awakhare

Manoj S. Awakhare, P.G. Student, Department of VLSI Design, Ramdeobaba College of Engineering, Nagpur (Maharashtra), India.
Manuscript received on 20 May 2014 | Revised Manuscript received on 25 May 2014 | Manuscript published on 30 May 2014 | PP: 49-53 | Volume-3 Issue-2, May 2014 | Retrieval Number: B1097053214/2014©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The design of A 2.4-GHz CMOS Class E cascode power amplifier (PA) for GSM applications in TSMC 0.18-μm CMOS technology present in this paper. Proposed Class E cascode PA topology is a single-stage topology in order to minimize the device stress problem. A parallel capacitor is connected across the transistors for efficiency enrichment also for dominating the effect of parasitic capacitances at the drain node. The simulation results point to that the PA delivers 12 dBm output power with 43.6% and 46.6% of power added efficiency (PAE) and drain efficiency (DE) respectively with 2.5-Volt power supply into a 50-Ω load
Keywords: Class E, CMOS Power amplifier, Power Added Efficiency, Switching Amplifier.

Scope of the Article: Routing, Switching and Addressing Techniques