Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation
Herman B. Acla1, Bobby D. Gerardo2 

1Herman B. Acla, Graduate School, Technological Institute of the Philippines, Quezon City, Philippines and Northern Iloilo Polytechnic State College, Iloilo, Philippines.
2Bobby D. Gerardo, Institute of Information and Communications Technology, West Visayas State University, Iloilo City, Philippines

Manuscript received on 01 March 2019 | Revised Manuscript received on 08 March 2019 | Manuscript published on 30 July 2019 | PP: 1810-1815 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1025078219/19©BEIESP | DOI: 10.35940/ijrte.B1025.078219
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Abstract: Advanced Encryption Standard (AES) is one of the most secured encryption algorithm because of its robustness and complexity. Because of its complexity, AES has slow computation. This paper presents a Lightweight Advanced Encryption Standard (LAES) design by replacing the MixColumn transformation of the traditional AES with a 128-bit permutation to lessen its computational complexity. Implementation of hardware cryptographic encryption aims to find the best trade-off between throughput and resource utilization. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and achieves the maximum clock frequency of 480.50 MHz with the highest throughput of 6.15 Gbps when synthesized on Virtex 7 XC7VX690T. The results on other devices show a higher throughput, better performance efficiency, and lesser area utilization when compared to the existing AES hardware implementation.
Index Terms: AES Algorithm, FPGA, Hardware Based Encryption, Permutation Table.

Scope of the Article: High Performance Computing