Performance Parameters of 3 Value 8t Cntfet Based Sram Cell Design Using H-Spice
S. Tamil Selvan1, M. Sundararajan2

1S. Tamil Selvan, Research Scholar, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
2M. Sundararajan, Dean-Research, Bharath Institute of Higher Education & Research, Chennai (Tamil Nadu), India.
Manuscript received on 13 July 2019 | Revised Manuscript received on 09 August 2019 | Manuscript Published on 29 August 2019 | PP: 22-27 | Volume-8 Issue-2S5 July 2019 | Retrieval Number: B10050682S519/2019©BEIESP | DOI: 10.35940/ijrte.B1005.0782S519
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Abstract: This paper presents a design of a 3ValueLogic 9T memory cell using carbon nano-tube field-effect transistors (CNTFETs). The carbon nano tubes with their superior transport properties, excellent current capabilities ballistic transport operation, 3-value logic have been proposed for 8T SRAM cell implementation in CNTFET technology. The CNTFET design to achieves the different threshold voltages. And it also avoids the usage of additional power supplies. The channel length used here is 18nm wide. The power consumption is reduced, as there is absence of stand-by power dissipation. Second order effects are removed by using CNTFET. In a 3 Value Logic, it only takes log3 (2n) bits to represent an n-bit binary number. In 3Value logic 9T memory cell based CNTFET have been developed and extensive HSPICE simulations have been performed in realistic environments. CNTFET 9T based SRAM cell proves which is Dynamic power better than CNTFET, based 3value logic 8T SRAM cell as well as CMOS SRAM cell.
Keywords: CNTFET, 3ValueLogic, HSPICE, Multi Threshold Value, FINFET, QDGFET, SNM, SWCNT.
Scope of the Article: Optical Link Design