Design of Physical Coding Sublayer using 8B/10B Algorithm
N. Kiran Babu1, P. S. Srinivas Babu2
1N.Kiran Babu, Research Group VLSI., Department of Electronics & Communication Engineering, KL University, Guntur (Andhra Pradesh), India.
2Dr. P.S. Srinivas Babu, Research Group VLSI., Department of Electronics & Communication Engineering, KL University, Guntur (Andhra Pradesh), India.
Manuscript received on 21 May 2013 | Revised Manuscript received on 28 May 2013 | Manuscript published on 30 May 2013 | PP: 114-117 | Volume-2 Issue-2, May 2013 | Retrieval Number: B0623052213/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Order to resolve the problem of base-line offset and unbalanced code flow during the fiber data transmission, thesis give a simple and practical solution 8B/10B encoder. This solution taking a method which integrate checking scheme and logic operation, through Verilog HDL description language, realize the design of encoder. The proposed circuit is simulated in Xilinx and Cadence. The results obtained in various tools are presented in this paper.
Keywords: Physical Coding Sub layer, 8B/10B Algorithm, Synchronization, Verilog HDL, Cadence Encounter.
Scope of the Article: Web Algorithms