VLSI Implementation of 2-D Discrete Wavelet Transformation using Reversible Logic Gates
P. Kowsalya1, S. M. Sakthivel2
1P. Kowsalya, SENSE, VIT University, Chennai, (Tamil Nadu), India.
2S. M. Sakthivel, SENSE, VIT University, Chennai, (Tamil Nadu), India.

Manuscript received on 08 April 2019 | Revised Manuscript received on 14 May 2019 | Manuscript published on 30 May 2019 | PP: 1621-1629 | Volume-8 Issue-1, May 2019 | Retrieval Number: A5588058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The two-dimensional Discrete Wavelet Transform (DWT) has received much attention over the last two decades in many multimedia applications such as MPEG-4 processing, JPEG2000 based compression, information retrieval systems and digital image watermarking. Therefore in the present work rather than implementing the DWT using conventional convolution based methodology, a Lifting and Haar wavelet based realization is incorporated to reduce the storage of algorithm and computational complexity. Furthermore the delay, power and efficiency of the DWT architecture are reduced and increased respectively by implementing the proposed architecture using reversible logic gates. Also the implementation of reversible logic gates based DWT structure preserves the data integrity without any loss of information during image processing adding together a parallel & pipelined architecture of the Haar wavelet DWT is implemented in this paperwork using “ gpdk 180nm” technology. The overall ASIC implementation of reversible DWT using cadence EDA tool consumes an area of 406.45.5 sq.μm , delay of 2.169ns & power of 14808.103nW.
Index Terms: Reversible Logic Gates, 2-D DWT, Haar Wavelet, Lifting Scheme, ASIC & Cadence EDA ® Tools.
Scope of the Article: VLSI Algorithms