Ordinary and Extraordinary Leakage Suppression Techniques for the Designing of SRAM Sense Amplifiers
Deepak Mittal1, V. K. Tomar2
1Deepak Mittal, Assistant Professor in GLA University Mathura from 2015.
2V. K. Tomar, Asst. Professor in Department of Electronics and Communication Engineering, GLA University, Mathura.

Manuscript received on 20 April 2019 | Revised Manuscript received on 24 May 2019 | Manuscript published on 30 May 2019 | PP: 1366-1373 | Volume-8 Issue-1, May 2019 | Retrieval Number: A3143058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In present paper ordinary and extra ordinary techniques have been implemented in 180nm technology gpdk using Cadence virtuoso tool. Current century, the development of microprocessors is a challenging issue due to high power consumption. This high power consumption generally depends on static power and dynamic power consumption but in today scenario leakage power dissipation participate an important role in high power consumption. Memory contains a wide area of microprocessor that means leakage power consumption will be more in memory. In proposed work, it has been observed that the current sense amplifier consume 79% less power as compare to charge transfer and 56% less power as compare to the high speed sense amplifier. Furthermore, it has been found that Row by Row Voltage Approach for Leakage Power Reduction technique reduces the leakage power dissipation up to 99 percent in current sense amplifier and high speed sense amplifier. In charge transfer sense amplifier triple stack technique reduces the leakage power dissipation up-to 99 percent. In Extraordinary leakage power reduction technique leakage current can be measure using leakage sensor in the range of 10 nA to 1μA. Due to this technique required area of memory reduces up to eight percent.
Index Terms: Extraordinary Leakage Power Reduction Technique (ELPRT), Footer Stack Technique (FST), Modified Body Biasing Technique (MBBT), Power Gating Techniques, Row by Row Voltage Approach for Leakage Power Reduction (RRVALPR), SRAM System With Proposed Adiabatic Driver Circuit (SSWPADC).

Scope of the Article: Knowledge Engineering Tools and Techniques