Design of Low Power Adder Cell by XOR & XNOR Gate
Rahul Jadia1, Sonali Joshi2

1Rahul Jadia, PG Scholar, Department of Electronics Engineering, G H Raisoni college of Engineering, Nagpur, India.
2Sonali Joshi, Assistant Professor, Department of Electronics Engineering, G H Raisoni college of Engineering, Nagpur, India.

Manuscript received on May 18, 2020. | Revised Manuscript received on May 27, 2020. | Manuscript published on May 30, 2020. | PP: 2560-2564 | Volume-9 Issue-1, May 2020. | Retrieval Number: A3026059120/2020©BEIESP | DOI: 10.35940/ijrte.A3026.059120
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Abstract: In under this research article, neoteric circuits for Exclusive OR gate and Exclusive NOR gate are designed. The designed logic is highly refined in terms of power consummation and speed, which are due to minimum CL at the output and low leakage power. We followed six novel hybrids, one bit one full-adder design based on the new Exclusive OR gate and Exclusive NOR (XOR-XNOR) gates. Many Relevant designed logics carries its advantages within aspect relevant to delay power, dissipation power, speed, as well as all that. Within validate the presentation of the introduced design, major SPICE as well as Tanner EDA simulations function as executed. This simulation outcomes, arrange at a 65-nanometer based on hybrid technique process, reveal for the introduced architecture have the best speed and power in contempt of different Full Adder architectures. The proposed design has a minimum power of 0.8 nw & delay of 9.4 ns, which is very optimized & efficient than the reference design. The previous design has 4.08-microwatt power. We customized the design with 22T and change the design methodology to make the results optimized. 
Keywords: Tanner EDA, Power, Delay, Digital Circuit Design, Power Optimization, CMOS, Pass Transistor, Full adder (FA), XOR-XNOR, Transistor (T), Hybrid Full Adder (HFA) [14], Sleepy-Gate Diffusion Input (S-GDI) [20], Complementary Pass Transistor Logic (CPTL) [20], Economized Pass Transistor Rationale (EEPL) [20], Differential Cascade Voltage (DCV) [20], Pass Transistor Logic (PTL) [20], Transmission Gate (TG), Complementary CMOS technique (CCT) [20].
Scope of the Article: Wireless Power Transmission