Performance Measures of Different Gate Oxide Materials in Gate All Around Fet
S. Ahmad Saidulu1, R.Sai Vineeth2, Y.Tanmayee3, B.Meenakshi4

1S.Ahmad Saidulu, Asst.Prof, ECE,K L University, Vijayawada, India.
2R.Sai Vineeth, ECE,K L University, Vijayawada, India.
3Y. Tanmayee, ECE,K L University, Vijayawada, India.
4B.Meenakshi, ECE,K L University, Vijayawada, India. 

Manuscript received on May 25, 2020. | Revised Manuscript received on June 29, 2020. | Manuscript published on July 30, 2020. | PP: 23-25 | Volume-9 Issue-2, July 2020. | Retrieval Number: A2626059120/2020©BEIESP | DOI: 10.35940/ijrte.A2626.079220
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Abstract: The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET’s so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials. 
Keywords: Gaafet’s; Gate Materials; Short Channel Effect (Sce); Sensitivity