DWT Chip Design and FPGA Synthesis for Image Processing
Arvind Bisht1, Adesh Kumar2
1Arvind Bisht, Department of Electronics & Communication Engineering, National Institute of Technology (NIT), Pauri Garhwal, Uttarakhand, India.
2Adesh Kumar Department of Electrical & Electronics Engineering, School of Engineering, University of Petroleum and Energy Studies, Dehradun, India.

Manuscript received on 22 April 2019 | Revised Manuscript received on 27 May 2019 | Manuscript published on 30 May 2019 | PP: 2526-2532 | Volume-8 Issue-1, May 2019 | Retrieval Number: A2204058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The wavelet transforms are used for the detection, extraction, de-noising, compression and analysis of signals and images. A Discrete Wavelet Transform (DWT) is the wavelet transform in which the wavelets are discretely sampled. HAAR DWT is one the popular method of image compression as its coefficients are either 1 or -1. In the DWT, the filters are half band about the quadrature frequency of radians per sample. The image is decomposed in LL, LH, HL and HH subbands in HAAR DWT method. The research paper focuses on the design and chip implementation of 2D-DWT using VHDL programming in Vivado Design Suite 17.4 and its synthesis on Virtex 5 FPGA. The 2D original image (64 x 64) is processed in (32 x 32) size LL, LH, HL and HH subbands in level 1 decomposing and further 16 x 16 subbands decomposition in level-2 processing. The FPGA hardware utilization and Timing parameters are analyzed for the design.
Index Terms: VHDL Programming, Discrete Wavelet Transform (DWT), FPGA Synthesis

Scope of the Article: Signal and Image Processing