Design and FPGA Implementation of LDPC Decoder Chip for Communication System using VHDL
Aakanksha Devrari1, Adesh Kumar2, Himanshu Chauhan3, Amit Kumar4 

1Aakanksha Devrari, Research Scholar, Department of Electronics & Communication Engineering, Uttarakhand Technical University, Dehradun, India.
2Adesh Kumar Department of Electrical & Electronics Engineering, University of Petroleum and Energy Studies, Dehradun, India.
3Himanshu Chauhan, Department of Electronics & Communication Engineering, College of Engineering (COER), Roorkee India.
4Amit Kumar Faculty of Technology, Uttarakhand Technical University, Dehradun, India.

Manuscript received on 11 March 2019 | Revised Manuscript received on 18 March 2019 | Manuscript published on 30 July 2019 | PP: 200-206 | Volume-8 Issue-2, July 2019 | Retrieval Number: A2203058119/19©BEIESP | DOI: 10.35940/ijrte.A2203.078219
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Abstract: The paper emphasized on the design and application of LDPC coding system using FPGA. The LDPC decoder is used to decode the information/data received from the channel after correcting channel errors based on parity bits selection of the data bits. In the communication system, when a parity check failure is noticed, the information from the multiple parity bits can be used to recover the original data bit. The LDPC decoder implementation is done using Shift-Register based design to reduce the complexity. The Modified Sum Product (MSP) method is used to decode, the signal. The system performance is also analyzed with hardware chip and timing parameters with FPGA implementation of the same system. The chip design of the LDPC chip is done usingVivado 17.4, programmed with the use of VHDL and hardware performance is estimated on Virtex-5 FPGA.
Index Terms: AWGN, BPSK, LDPC Codes, VHDL Language, MSP, FPGA

Scope of the Article: Wireless Communication