An Innovative Technique to Protect a Register File from Multiple-bit-Upsets Implemented on FPGA
Ravi Dontaraju1, S. Bhujanga Rao.2
1Ravi Dontaraju, Department of Electronics and Communication Engineering, Sreenidhi institute of Science and technology, Hyderabad, India.
2S. Bhujanga Rao, Professor, Director-SOE, Department of Electronics and Communication Engineering, Sreenidhi institute of Science and technology, Hyderabad, India.
Manuscript received on 16 April 2019 | Revised Manuscript received on 21 May 2019 | Manuscript published on 30 May 2019 | PP: 1743-1748 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1847058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The development of electronic devices which possess a characteristic to resist radiation-induced upsets is an active area of research in the semiconductor industry. There are several techniques beginning from the manufacturing level of the transistors to the implementation level of a chip, which helps in masking or eliminating faults caused by radiation. In this paper, an implementation level technique is proposed which can mask multiple bit-upsets caused by radiation in a register file implemented on an FPGA. The advantage of this technique is that masking of the errors is done by leveraging the inherent resources present in an FPGA due to which there shall be a significant decrease in the area overhead without a compromise in the reliability and delay of the system.
Index Terms: Faults, FPGA, Radiation-Induced Upsets, Reliability, Semi-Conductor.
Scope of the Article: Structural Reliability Analysis