FPGA Implementation of Contention Free Turbo Decoder for Wireless Communications
Chaithanya Kumar M1, J Manjula2
1Chaithanya Kumar M, Department of VLSI Design at SRM Institute of Science and Technology
2J. Manjula, Department of Electronics and Communication Engineering, SRM University.

Manuscript received on 08 April 2019 | Revised Manuscript received on 16 May 2019 | Manuscript published on 30 May 2019 | PP: 3368-3371 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1809058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Higher data rates were supported by long term evolution (LTE). When there is higher data rates, error detection and correction of the data goes complex. To solve that problem turbo codes are much efficient. By parallelizing the required procession in turbo decoders, effective high rates are achieved and it reaches the channel capacity much better than other codes. In turbo decoder an interleaver plays a crucial role. An interleaver is much preferable for LTE is Quadratic Permutation Polynomial (QPP). It makes the interleaver which is appropriate in parallel decoding. In this paper, a simple Add-compare-select (ACS) network is proposed instead of QPP interleaver which is efficient. The proposed architecture can be used as both interleaver and deinterleaver. The hardware interleaver is used for high speed low complexity. In turbo coding deinterleaver is used. For the proposed interleaver/deinterleaver doesn’t require any memory. The implementation of turbo encoder and turbo decoder is done by a Virtex-6 FPGA and compared the result with QPP interleaver.
Index Terms: Add-Compare-Select Network, FPGA, Interleaver, LTE, Parallel Decoding, QPP, Turbo Decoder.

Scope of the Article: Wireless Communications