Design and Analysis of 8-bit Low Power Parallel Prefix VLSI Adder
Shrinivas K Saptalakar1, Manjunath Lakkannavar2

1Mr. Shrinivas K Saptalakar, VLSI and Embedded Systems, VTU Extension Centre UTL Technologies Ltd., Bangalore (Karnataka), India.
2Prof. Manjunath Lakkannavar, VLSI and Embedded Systems, VTU Extension Centre, UTL Technologies Ltd., Bangalore (Karnataka), India.
Manuscript received on 21 March 2013 | Revised Manuscript received on 28 March 2013 | Manuscript published on 30 March 2013 | PP: 141-144 | Volume-2 Issue-1, March 2013 | Retrieval Number: A0537032113/2013©BEIESP
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Abstract: The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. High speed and low power Arithmetic units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. The present work focused on designing of high performance low power 8-bit parallel prefix adder structure. For improving the speed and to reduce the power, we have reduced the static power and dynamic power. The design is simulated using Xilinx 13.2 ISE and implemented on Spartan 3 FPGA Board.
Keywords: Parallel Prefix Adder, Propagation Signal, Power, Delay

Scope of the Article: Predictive Analysis