A Comparative Study of Different Low Power Techniques for SRAM
Patel Henalkumari D1, Rachna Jani2, Jaymin Bhalani3
1Patel Henalkumari D., PG. Student, V. T. Patel Department of Electronics & Communication, Chandu bhai S. Patel Institute of Technology, Changa Anand (Gujarat) India.
2Associate professor Rachana Jani, V.T.Patel Department of Electronics & Communication, Chandu bhai S. Patel Institute of Technology, Changa, Anand (Gujarat) India.
3Associate professor Jaymin bhalani V.T. Patel department of Electronics & communication, Chandubhai S. Patel Institute of Technology – Changa, Anand, Gujarat India.
Manuscript received on 18 April 2012 | Revised Manuscript received on 25 April 2012 | Manuscript published on 30 April 2012 | PP: 54-58 | Volume-1 Issue-1, April 2012 | Retrieval Number: A0143021112/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: There is three type of low power technique discussed here for Static random access memory. One is Quiet Bit line architecture in which the voltage of bit line stay as low as possible. To prevent the excessive full-swing charging on the bitline one-side driving scheme for write operation is used and for read precharge free-pulling scheme is used to keep all bit lines at low voltages at all times. Second is Body bias technique which decreases the process variation on the SRAM cell and it can operate at 0.3 and write margin is not degraded. Third is half –swing Pulse-mode techniques in which Halfswing Pulse-mode gate family is used that uses reduced input signal swing without sacrificing performance and to save the power, bit lines are operated from V /2 dd instead of Vdd .
Keywords: Low power, SRAM, Body Biasing, Quiet Bit line, Half-Swing Pulse-Mode, Low voltage.
Scope of the Article: Low-power Design