Design of Bootstrap Sample and Hold Circuit
Ankush Chunn
Ankush Chunn, Department of Electronics and Communication, National Institute of Technology, Raipur, Chattisgarh, India. 

Manuscript received on November 10, 2019. | Revised Manuscript received on November 17, 2019. | Manuscript published on 30 November, 2019. | PP: 4053-4058 | Volume-8 Issue-4, November 2019. | Retrieval Number: D8462118419/2019©BEIESP | DOI: 10.35940/ijrte.D8462.118419
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Abstract: This paper describes the design and implementation of open loop sample and hold circuit using bootstrap technique, which can be used as front end sampling circuit for high speed analog-to-digital converters. Different design criteria viz. speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18μm and 0.35μm CMOS process. It is observed that signal to noise and distortion ratio (SNDR) and effective number of bits (ENOB) are higher for 0.35μm technology. But these advantages are at the cost of higher power dissipation. Hence there exists a trade-off between these performance metrics.
Keywords: Sample and Hold, Bootstrap.
Scope of the Article: Microstrip Antenna Design and Application.