Design and Power Analysis of Vedic Multiplier
S.Kiruthika1, P.Sakthi2, P.Yuvarani3
1S.Kiruthika*, Department of Electronics and Instrumentation Engineering, M.Kumarasamy College of Engineering, Karur, India.
2P.Sakthi, Department of Electronics and Instrumentation Engineering, M.Kumarasamy College of Engineering, Karur, India.
3P.Yuvarani, Department of Electronics and Instrumentation Engineering, M.Kumarasamy College of Engineering, Karur, India.
Manuscript received on 1 August 2019. | Revised Manuscript received on 9 August 2019. | Manuscript published on 30 September 2019. | PP: 2961-2966 | Volume-8 Issue-3 September 2019 | Retrieval Number: C4809098319/2019©BEIESP | DOI: 10.35940/ijrte.C4809.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this article, displays the capacity of decrease the Power, Area in CMOS VLSI blocks. Power in CMOS circuits is mostly consumed for the duration of the transitions of the gates. Thusly, control estimation of CMOS circuits is changed over into progress action estimation. A few methods are utilized to mimic progress exercises of CMOS circuits. The proposed Vedic multiplier is planned by utilizing various strategies of full adder cells. The structure of full adders for low power is gotten and low power blocks are actualized on the arranged multiplier with the outcomes be broke down used for improved execution. The structures are finished by utilizing TANNER S-EDIT tool and recreated utilizing T-SPICE.
Keywords: CMOS, Full Adder, Vedic multiplier, Low power, XOR, XNOR, MUX.
Scope of the Article: Classification.