FPGA Implementation of Power-Efficient ECG Pre-Processing Block
Kirti1, Harsh Sohal2, Shruti Jain3
1Kirti, Department of Electronics and Communication, Jaypee University of Information Technology, Waknaghat, Solan, Himachal Pardesh, India.
2Harsh Sohal, Department of Electronics and Communication, Jaypee University of Information Technology, Waknaghat, Solan, Himachal Pardesh, India.
3Shruti Jain, Department of Electronics and Communication, Jaypee University of Information Technology, Waknaghat, Solan, Himachal Pardesh, India.

Manuscript received on 17 April 2019 | Revised Manuscript received on 23 May 2019 | Manuscript published on 30 May 2019 | PP: 2899-2904 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1461058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: TThe hardware implementation of a low power digital system design is proposed to pre-process the Electrocardiogram (ECG) using an FPGA board. The system implementation of the pre-processing module consists of removal of two prominent noises namely Electromyography and Base Line Wander using two different types of filters comprising Low Pass Filter and High Pass Filter. Model-Based design of Finite Impulse response filter is implemented using Xilinx System Generator targeting ZedBoard Zynq-7000 evaluation board using XILINX VIVADO tool. To obtain the optimized resource utilization and power consumption various conventional windows has been compared. Kaiser and Bartlett’s window shows the best performances as it utilizes only 0.41% of LUT and 0.37% of registers. These windows also consume only 35 mW of power in contrast to other windowing methods. The hardware implementation of the selected pre-processing module will be used in wearable and portable ECG module in the future.
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Scope of the Article: Energy Efficient Building Technology